The invention is in the field of metal-oxide-semiconductor (MOS) devices, and relates more specifically to combined lateral MOS/bipolar transistors suitable for use in both common-source and source-follower applications.
A typical prior-art high voltage DMOS transistor is shown on page 1325 of the "IEEE Transactions on Electron Devices", Vol. ED-25, No. 11, November 1978, in a paper entitled "Tradeoff Between Threshold Voltage and Breakdown in High-Voltage Double-Diffused MOS Transistors", by Pocha et al. This device includes a semiconductor substrate of a first conductivity type (p-type), a surface layer of a second conductivity type (n-type) on the substrate, a surface-adjoining channel region of the first conductivity type in the epitaxial layer, a surface-adjoining source region of the second conductivity type in the channel region, and a surface-adjoining drain contact region of the second conductivity type in the epitaxial layer and spaced apart from the channel region. An insulating layer is provided on the surface layer and covers at least that portion of the channel region located between the source and drain. A gate electrode is provided on the insulating layer, over a portion of the channel region between the source and drain and is electrically isolated from the surface layer, while source and drain electrodes are connected respectively to the source and drain regions of the transistor. Such prior-art high-voltage DMOS transistors have a relatively thick surface layer (typically an epitaxial layer), in the order of about 25-14 30 microns for a breakdown voltage of about 250 V, as indicated in the Pocha et al paper. Furthermore, the punchthrough and avalanche breakdown characteristics of these devices relative to their epitaxial layer thickness make them unsuitable for efficient use in applications requiring high voltages.
It has been found that the breakdown characteristics of high-voltage semiconductor devices can be improved using the REduced SURface Field (or RESURF) technique, as described in "High Voltage Thin Layer Devices (RESURF Devices)", "International Electronic Devices Meeting Technical Digest", December 1979, pages 238-240, by Appels et al, and U.S. Pat. No. 4,292,642 to Appels et al. Essentially, the improved breakdown characteristics of these RESURF devices are achieved by employing thinner but more highly doped epitaxial layers to reduce surface fields.
The RESURF technique was applied to lateral double-diffused MOS transistors, as reported in "Lateral DMOS Power Transistor Design", "IEEE Electron Device Letters", Vol. EDL-1, pages 51-53, April 1980, by Colak et al and U.S. Pat. No. 4,300,150, and the result was a substantial improvement in device characteristics. It should be understood that in high-voltage DMOS devices, there is always a trade-off between breakdown voltage, on-resistance and device size, with the goal being to increase the breakdown voltage level while maintaining a relatively low on-resistance in a relatively compact device. Using the prior-art RESURF technique, and for reference assuming a constant breakdown voltage of about 400 volts, a very substantial improvement (e.g. decrease) in on-resistance may be obtained in a device of the same size as a conventional (thick epitaxial layer) DMOS device.
However, such prior-art RESURF devices, with their thin epitaxial layers, are not suitable for use in source-follower applications or other circuit arrangements where both the source and drain are at a high potential with respect to the substrate. For such applications, these devices would require a substantially thicker epitaxial surface layer, thus negating a principal advantage of the RESURF technique and increasing device size and cost, or they would require a lower epitaxial doping level, which would increase "on" resistance, again negating a principal advantage of the RESURF technique.
A lateral double-diffused MOS transistor suitable for use in source-follower applications which maintains the advantages associated with the RESURF technique is disclosed in U.S. patent application Ser. No. 451,993 filed 12/21/82 to Colak. The devices disclosed by Colak use a three-layer configuration in which the intermediate layer is highly doped, and in which the semiconductor zone forming the channel region of the device is directly in contact with the lowermost layer of the three-layer structure. Although the Colak device is a substantial improvement over prior-art devices, it still requires application of the RESURF principle in both the vertical and horizontal directions in its most advantageous high-voltage configuration, is more complex and difficult to manufacture, and is limited in terms of the specific "on" resistance that can be achieved. Additionally, bipolar conduction is not possible in the Colak configuration because of large substrate leakage.